1. Field of the Invention
The present invention relates generally to cache memory systems, and more particularly relates to a cache memory architecture for selectively storing directory information corresponding to a higher level cache data array in at least a portion of a lower level cache data array.
2. Description of the Prior Art
It is well known in the art that the performance of a microprocessor system can be significantly improved by introducing a comparatively small but fast memory between the processor and main memory. Quite often, a small amount of cache memory (e.g., L1 cache) is included on-chip with the processor, with larger cache arrays being provided at one or more next higher levels external to the processor (e.g., L2 and L3 cache). The cache memory may be organized to include one or more directory arrays and corresponding data arrays. Directory arrays hold metadata which provides information relating to the data stored in the data arrays.
An important disadvantage with conventional cache memory systems, however, is that such cache systems have a fixed use and geometry (i.e., physical size), and therefore must be individually adapted to the architecture supported by the processor chip/module. Another disadvantage of conventional cache memory structures is that with the requirement for increasingly larger cache data arrays, the size of the corresponding directory arrays increases accordingly, thereby resulting in the need for larger cache memory systems which significantly increases the cost of the overall system.
There remains a need, therefore, in the field of cache memory systems for a cache memory architecture that can utilize at least portions of a lower level cache data array to selectively store directory information relating to a higher level cache data array.
The present invention is tantamount to a departure from the prior art because of the all-encompassing new characteristics. A system formed in accordance with the present invention revolutionizes the field of cache memory systems by selectively permitting the use of a conventional cache data array as a directory array for an off-chip data array of a higher level cache system. Using this unique architecture, several different off-chip cache topologies can be easily supported so as to meet the caching requirements of various systems and applications (e.g., high-end commercial, low-end commercial and scientific applications). These and other improvements and advantages of the present invention are made possible, at least in part, by including a secondary tag match unit operatively coupled to at least one conventional on-chip cache data array. The secondary tag match unit can be similar, at least in terms of design and function, to a conventional tag match typically associated with an on-chip cache directory.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings, wherein like elements are designated by identical reference numerals throughout the several views.